Techniques for Phase Detection

ABSTRACT

A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output  signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

CROSS REFERENCE TO RELATED APPLICATION

This patent application claims the benefit of U.S. provisional patentapplication 61/260,797, filed Nov. 12, 2009, which is incorporated byreference herein in its entirety.

TECHNICAL FIELD

The present invention relates to electronic circuits, and moreparticularly, to techniques for phase detection.

BACKGROUND

A phase detector circuit generates an output signal that is indicativeof the phase difference between two periodic input signals. A zero phasedetector ideally generates a zero output when the two periodic inputsignals are aligned in phase with each other. Zero phase detectors areused in many applications including delay-locked loops (DLLs). As datarates increase in modern data transmission systems, the DLLs inhigh-speed data transmission systems require faster zero phasedetectors. However, conventional zero phase detectors have a modestspeed limit before generating a hard failure.

High-speed zero phase detectors have complex circuit architectures thatconsume a large amount of power and die area. An XOR based quadraturephase detector can operate at a relatively high speed, but it generatesa zero output signal when the periodic input signals are 90 degrees outof phase. Therefore, it would be desirable to provide a similarlyhigh-speed zero phase detector that generates a zero output signal whenthe periodic input signals are in phase and that does not have many ofthe problems of conventional zero phase detectors.

It would also be desirable to provide a high-speed delay-locked loop(DLL) that converges to the point at which the periodic input signals ofthe phase detector are aligned in phase. In one type of DLL, thefrequency of a high-speed reference clock signal is divided by an inputfrequency divider circuit to generate a lower speed clock signal. Thelower speed clock signal is provided to the input of a low speed phasedetector in the DLL. The input frequency divider circuit consumes asignificant amount of power and generates a substantial amount of jitterin the output clock signal. Therefore, it would be desirable to providea high-speed DLL that consumes less power and generates less jitter inthe output clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a circuit that generates a zero outputwhen the phases of two periodic input signals are aligned.

FIG. 2A illustrates an example of a high-speed phase detection circuitthat uses two quadrature phase detectors and two delay circuits togenerate a zero output in response to the phases of two periodic inputsignals being aligned.

FIG. 2B is a graph of the output voltage response of a quadrature phasedetector plotted over the phase difference (φ) between two periodicinput signals to the quadrature phase detector.

FIG. 2C is a graph that shows an example of the output voltage responsesof the quadrature phase detectors in FIG. 2A plotted over the phasedifference (φ) between the periodic input signals to the phasedetectors.

FIG. 2D is a graph that shows an example of the output voltage responseof the phase detection circuit of FIG. 2A plotted over the phasedifference (φ) between the periodic input signals.

FIG. 3 illustrates another example of a phase detection circuit thatuses two quadrature phase detectors to generate a zero output inresponse to the phases of two periodic input signals being aligned.

FIG. 4 illustrates an example of a phase detection circuit that uses twozero phase detectors having static phase offsets to generate a zerooutput in response to the phases of two periodic input signals beingaligned.

FIG. 5 illustrates an example of a phase detection circuit thatfunctions as a zero phase detector using chopper switches, a quadraturephase detector, and sample and hold circuits.

FIG. 6A illustrates an example of a phase detection circuit thatgenerates a continuous time output signal using switches and aquadrature phase detector.

FIG. 6B illustrates one example of a current mode logic (CML) XORcircuit implementation of the phase detection circuit shown in FIG. 6A.

FIG. 7 illustrates an example of a phase detection circuit that samplestwo periodic input signals and then subtracts the sampled values togenerate a phase comparison signal.

FIG. 8A illustrates an example of a delay-locked loop (DLL) circuit thatcan include one of the phase detection circuits shown in FIGS. 1, 2A, 3,4, 5, 6A-6B, and 7.

FIG. 8B illustrates an example of a phase-locked loop (PLL) circuit thatcan include one of the phase detection circuits shown in FIGS. 1, 2A, 3,4, 5, 6A-6B, and 7.

FIG. 9 illustrates an example of a delay-locked loop (DLL) circuit thataligns the phase of a feedback clock signal with the phase of areference clock signal using a quadrature phase detector.

FIG. 10 illustrates a schematic diagram of a differential current modelogic (CML) XOR based phase detector circuit that can be used as a phasedetector in the DLL of FIG. 9.

FIG. 11 is a graph that illustrates the output response of the phasedetector shown in FIG. 10.

DETAILED DESCRIPTION

As described herein, a phase detection circuit can function as ahigh-speed zero phase detector. The phase detection circuit does notrequire a large amount of die area or a large amount of powerconsumption. According to some embodiments, the phase detection circuitincludes two high-speed phase detectors. Each of the high-speed phasedetectors generates a non-zero output in response to input signals tothe phase detector being aligned in phase. The input signals to thephase detectors are based on two periodic signals. The phase detectioncircuit subtracts the output signal of one of the phase detectors fromthe output signal of the other phase detector to generate a phasecomparison signal having a zero value when the periodic signals arealigned in phase.

In other embodiments, a phase detection circuit includes a chopperswitch circuit, a delay circuit, and a high-speed phase detector. Thechopper switch circuit periodically switches input signals betweenoutputs of the chopper switch circuit. The delay circuit delays a firstoutput signal of the chopper switch circuit to generate a delayedsignal. The high-speed phase detector compares a phase of the delayedsignal with a phase of a second output signal of the chopper switchcircuit to generate an output signal. The output signal of the phasedetector has a non-zero value in response to the delayed signal and thesecond output signal of the chopper switch circuit being aligned inphase. An output signal of the phase detection circuit has a zero valuein response to the input signals of the chopper switch circuit beingaligned in phase.

FIG. 1 illustrates an example of a circuit 100 that generates a zerooutput when the phases of two periodic input signals are aligned.Circuit 100 has a phase detection block 101 that compares the phases oftwo periodic input signals A and B to generate a first phase comparisonsignal VC. Phase detection block 101 also compares the phases ofperiodic input signals A and B to generate a second phase comparisonsignal VD. Phase detection block 101 can include, for example, one ortwo constituent phase detectors that generate signals VC and VD. Each ofthe constituent phase detectors generates a non-zero output in responseto input signals to the phase detector being aligned in phase. Acombiner circuit 102 combines phase comparison signals VC and VD togenerate a third phase comparison signal OUT that has a zero value whenperiodic input signals A and B are aligned in phase.

FIG. 2A illustrates an example of a high-speed phase detection circuitthat uses two quadrature phase detectors and two delay circuits togenerate a zero output in response to the phases of two periodic inputsignals being aligned. Phase detection circuit 200 includes two delaycircuits 201-202, two high-speed quadrature phase detectors 203-204, anda subtraction circuit 205. A and B represent two periodic input signals.Signals A and B can be, for example, clock signals. Signals A and B havethe same frequency.

Signal A is provided to a first input of quadrature phase detector 203.Delay circuit 201 delays signal B by about 90° (i.e., about one-quarterof the period of signal B) to generate a delayed periodic signal BD thatis provided to a second input of quadrature phase detector 203. Phasedetector 203 generates an output phase comparison voltage signal VC thatis indicative of the phase difference between input signals A and BD.

Delay circuit 202 delays signal A by about 90° (i.e., about one-quarterof the period of signal A) to generate a delayed periodic signal AD thatis provided to a first input of quadrature phase detector 204. Signal Bis provided to a second input of quadrature phase detector 204. Phasedetector 204 generates an output phase comparison voltage signal VD thatis indicative of the phase difference between input signals AD and B.

According to alternative embodiments of phase detection circuit 200,quadrature phase detectors 203-204 are replaced with phase detectorsthat generate zero output signals when the phases of their periodicinput signals have a phase offset other than 0° or 90°, and delaycircuits 201-202 have delays that equal or approximately equal the phaseoffset.

FIG. 2B is a graph of the output voltage response of a quadrature phasedetector, such as phase detectors 203 and 204, plotted over the phasedifference (φ) between two periodic input signals to the quadraturephase detector. As shown in FIG. 2B, the output voltage signal of aquadrature phase detector is zero when the input signals to thequadrature phase detector have a phase difference of +90° or −90°. Whenthe periodic input signals of a quadrature phase detector are aligned inphase (i.e., have a 0° phase difference), the output voltage signal ofthe phase detector reaches a peak value.

FIG. 2C is a graph that shows an example of the output voltage responsesVC and VD of quadrature phase detectors 203 and 204, respectively,plotted over the phase difference (φ) between periodic signals A and B.Because signal B is delayed by about 90° before being provided to aninput of phase detector 203 as delayed signal BD, the output voltage VCof phase detector 203 reaches a peak value (i.e., an inflection point)when the phase difference between signals A and B is about 90°. When thephase difference between signals A and B is 0°, the output voltage VC ofphase detector 203 is near zero. The output voltage VC of phase detector203 may be zero when the phase difference between A and B is slightlypositive or slightly negative, as shown in FIG. 2C, depending on thedelay of circuit 201.

Because signal A is delayed by about 90° before being provided to aninput of phase detector 204 as delayed signal AD, the output voltage VDof phase detector 204 reaches a peak value (i.e., an inflection point)when the phase difference between signals A and B is about −90°. Whenthe phase difference between signals A and B is 0°, the output voltageVD of phase detector 204 is near zero. Output voltage VD may be zerowhen the phase difference between signals A and B is slightly positive,as shown in FIG. 2C, or slightly negative, depending on the delay ofcircuit 202.

Referring again to FIG. 2A, subtraction circuit 205 subtracts the outputvoltage VD of phase detector 204 from the output voltage VC of phasedetector 203 to generate the output voltage signal OUT of phasedetection circuit 200. Thus, VC−VD=OUT.

FIG. 2D is a graph that shows an example of the output voltage responseOUT of phase detection circuit 200 plotted over the phase difference (φ)between periodic input signals A and B. As shown in FIG. 2D, phasedetection circuit 200 generates a zero output voltage in OUT in responseto a phase difference of 0° between periodic input signals A and B.Phase detection circuit 200 causes output voltage OUT to be greater thanzero in response to a phase difference between A and B that is between0° and 180° (that is, periodic signal A lags periodic signal B bybetween 0° and) 180°). Phase detection circuit 200 causes output voltageOUT to be less than zero in response to a phase difference between A andB that is between −180° and 0°. Phase detection circuit 200 uses twohigh-speed quadrature phase detectors 203-204 to create a circuit thatfunctions as a high-speed zero phase detector, as shown in FIG. 2D.

Delay circuits 201-202 do not need to generate a precise delay of 90° insignals AD and BD. Phase detection circuit 200 functions as a zero phasedetector that generates a zero value in OUT when A and B are aligned inphase, even if delay circuits 201-202 generate delays in BD and AD thatare greater than or less than 90°. For example, phase detection circuit200 may continue to function as a zero phase detector over a range ofvariations of the delay of each of circuits 201-202 from 45° to 135°. Insome embodiments, phase detection circuit 200 may have an even widerzero phase detection range for variations of the delays of circuits201-202 that are greater than +/−45°.

Delays circuits 201 and 202 have matching delays. Delay circuits 201 and202 have the same circuit and layout designs, so that process, voltage,and temperature (PVT) variations cause the delays of circuits 201-202 tovary by the same amount. Phase detectors 203 and 204 have the samecircuit and layout designs. As a result, variations in output voltagesVC and VD track each other within a particular range (e.g., −45°<φ<45°)Subtraction circuit 205 cancels out PVT induced variations in VC and VDnear φ=0° so that OUT continues to have a zero voltage crossing at φ=0°.

Delay circuits 201-202 can be any arbitrary delay circuits, such as,delay chains of inverters, active buffer circuits,resistor/capacitor/inductor (RLC) filter circuits, transmission lines,etc. Each of the phase detectors 203-204 can be, for example, anexclusive OR (XOR) based quadrature phase detector that generates a zerooutput when the phase difference between its input signals is 90°.Subtraction circuit 205 can be an analog circuit or a digital circuit.

Phase detection circuit 200 can be used in a wide variety ofapplications. For example, phase detection circuit 200 and other phasedetection circuits described herein can be used in delay-locked loopscircuits (DLLs), in phase-locked loops circuits (PLLs), in clock datarecovery circuits, or in other loop circuit designs. If phase detectioncircuit 200 uses high-speed XOR based quadrature phase detectors203-204, a DLL or PLL that uses phase detection circuit 200 can achievea higher reference clock frequency than conventional zero phasedetectors. A DLL or PLL using phase detection circuit 200 can, forexample, be designed to increase the phase of signal B when the phasedifference between signals A and B is positive, and decrease the phaseof signal B when the phase difference between signals A and B isnegative. In this PLL/DLL example, the phase difference between signalsA and B converges to 0° when the phase difference between A and B isbetween −180° and 180°. The lock range for the DLL or the PLL in thisexample is −180°<φ<180°.

FIG. 3 illustrates another example of a phase detection circuit 300 thatuses two quadrature phase detectors to generate a zero output inresponse to the phases of two periodic input signals A and B being inalignment. Phase detection circuit 300 includes four delay circuits301-304, two quadrature phase detectors 305-306, and subtraction circuit307.

Each of delay circuits 301 and 304 has a delay of about 45°. Each ofdelay circuits 302 and 303 has a delay of about −45°. A delay circuitgenerating a negative delay (e.g., −45° can be constructed, for example,using LC filters. 45° refers to one-eighth of a period of input signalsA and B. In an alternative embodiment of phase detection circuit 300,each of delay circuits 301 and 304 has a delay of about −45°, and eachof delay circuits 302 and 303 has a delay of about 45°.

Delay circuit 301 delays input signal A by about 45° to generate delayedsignal A1 at an input of phase detector 305. Delay circuit 302 delaysinput signal B by about −45° to generate delayed signal B1 at an inputof phase detector 305. Delay circuit 303 delays input signal A by about−45° to generate delayed signal A2 at an input of phase detector 306.Delay circuit 304 delays input signal B by about 45° to generate delayedsignal B2 at an input of phase detector 306.

Phase detector 305 generates an output phase comparison voltage signalVC that is indicative of the phase difference between input signals A1and B1. Phase detector 306 generates an output phase comparison voltagesignal VD that is indicative of the phase difference between inputsignals A2 and B2. Each quadrature phase detector 305-306 generates azero output voltage VC/VD in response to the input signals to thatquadrature phase detector having a phase difference of +90° or −90°.

Subtraction circuit 307 subtracts output voltage VD from output voltageVC to generate the output voltage signal OUT of phase detection circuit300. Phase detection circuit 300 functions as a zero phase detector thatgenerates a zero output when the phase difference between signals A andB is 0°, even if delay circuits 301 and 304 generate matching delays insignals A1 and B2 that are slightly greater than or slightly less than45°, and delay circuits 302 and 303 generate matching delays in signalsB1 and A2 that are slightly greater than or slightly less than −45°. Thegraph of FIG. 2D is also an example of the output voltage response OUTof phase detection circuit 300.

FIG. 4 illustrates an example of a phase detection circuit 400 that usestwo zero phase detectors having systematic non-ideal static phaseoffsets to generate a zero output in response to the phases of twoperiodic input signals A and B being aligned. Phase detection circuit400 includes non-ideal zero phase detectors 401-402 with static offsetsand subtraction circuit 403. Non-ideal phase detectors 401 and 402generate phase comparison voltage signals VC and VD, respectively, thatare indicative of the phase difference between periodic input signals Aand B. Subtraction circuit 403 subtracts VD from VC to generate outputsignal OUT.

Non-ideal zero phase detectors 401-402 generate systematic static phaseoffsets in their output signals VC and VD. The static phase offsetscause detectors 401-402 to generate non-zero voltages in VC and VD inresponse to a phase difference of 0° between signals A and B. Thedetector output voltages VC and VD therefore respond as shown in FIG.2C, with a systematic non-zero output when the input phase difference φis 0°. However, the detector output voltages VC and VD of non-idealphase detectors 401-402 may not peak near 90° as shown in FIG. 2C. Suchnon-ideal zero phase detectors may operate faster than accurate zerophase detectors without such systematic static phase offsets.

Non-ideal zero phase detectors 401-402 have the same circuit designs. Asa result, PVT induced variations in the phase comparison signals VC andVD track each other, and subtraction circuit 403 cancels out the effectsof these variations on output signal OUT.

Phase detection circuit 400 generates an output signal OUT having zerovolts in response to a phase difference of 0° between signals A and B.Phase detection circuit 400 functions as a zero phase detector using twonon-ideal zero phase detectors that do not generate zero outputs inresponse to the phases of their input signals being aligned.

FIG. 5 illustrates an example of a phase detection circuit 500 thatfunctions as a zero phase detector using one or more chopper switches, aquadrature phase detector, and sample and hold circuits. Phase detectioncircuit 500 generates a zero output in response to two periodic inputsignals A and B being aligned in phase. Phase detection circuit 500includes chopper switches 501-502, delay circuit 503, quadrature phasedetector 504, sample and hold (S/H) circuits 505-506, and subtractioncircuit 507.

Each of the chopper switches described herein periodically switches itsinput signals between the two outputs of the chopper switch incontinuously alternating time periods. In circuit 500, chopper switches501-502 alternately route periodic input signals A and B through delaycircuit 503 based on the period of a digital clock signal CLK. Clocksignal CLK controls the switching period and duty cycle of choppersswitches 501-502. Chopper switches 501-502 eliminate the need for asecond quadrature phase detector in circuit 500.

When clock signal CLK is in a first logic state, chopper switches501-502 transmit signal A directly to the 1 input of phase detector 504via conductor 508. Also, when CLK is in the first logic state, chopperswitch 501 transmits signal B to an input of delay circuit 503, delaycircuit 503 delays signal B by about 90° to generate a delayed versionof signal B, and chopper switch 502 transmits the delayed version ofsignal B to the 2 input of phase detector 504. In this logic state,input signals A and B are connected to quadrature phase detector 504 ina manner similar to phase detector 203 in FIG. 2A.

When clock signal CLK is in a second logic state, chopper switches501-502 transmit signal B directly to the 2 input of phase detector 504via conductor 508. Also, when CLK is in the second logic state, chopperswitch 501 transmits signal A to the input of delay circuit 503, delaycircuit 503 delays signal A by about 90° to generate a delayed versionof signal A, and chopper switch 502 transmits the delayed version ofsignal A to the 1 input of phase detector 504. In this logic state,input signals A and B are connected to quadrature phase detector 504 ina manner similar to phase detector 204 in FIG. 2A.

Quadrature phase detector 504 generates a phase comparison voltagesignal VX that is indicative of the phase difference between theperiodic signals at its 1 and 2 inputs. Sample and hold circuits 505 and506 sample the voltage of signal VX to generate sampled signals VY andVZ, respectively. The sampling rates of circuits 505 and 506 are basedon the timing of clock signals CLK and CLKB, respectively. Circuit 505samples VX when CLK is in a first logic state, and circuit 506 samplesVX when CLKB is in the first logic state. Clock signals CLK and CLKB are180° out of phase with each other. Circuit 505 holds the previouslysampled state of VX as signal VY when CLK is in a second logic state,and circuit 506 holds the previously sampled state of VX as signal VZwhen CLKB is in the second logic state.

The sampling rate of circuits 505-506 is the same as the switching rateof chopper switches 501-502. The CLK signal typically has a lowerfrequency than the A and B input signals, so that after the CLK logicstate changes, quadrature phase detector 504 has sufficient time todevelop an accurate phase measurement before the result is sampled andthe CLK logic state changes again. Sample and hold circuits 505 and 506are intended to sample the voltage of signal VX just before the CLKlogic state changes, to avoid sampling VX during a transition period.Sampling VX during a transition period can be avoided, for example, byclocking sample and hold circuits 505 and 506 using an earlier versionof CLK and CLKB than is used to switch chopper switches 501 and 502.

Subtraction circuit 507 subtracts the voltage of signal VZ from thevoltage of signal VY to generate output signal OUT (i.e., VY−VZ=OUT).Phase detection circuit 500 generates a zero in output signal OUT whenthe phase difference between periodic input signals A and B is 0°.However, the output signal OUT of circuit 500 may become discontinuouseach time clock signal CLK changes state. Quadrature phase detector 504may have a phase response as shown in FIG. 2B that is insensitive towhich of the two input signals has an earlier phase and is onlysensitive to the magnitude of the phase difference. Therefore, chopperswitch 502 may be removed in some embodiments.

FIG. 6A illustrates an example of a phase detection circuit 600 thatgenerates a continuous time output signal using switches and aquadrature phase detector. Phase detection circuit 600 functions as azero phase detector that generates a zero output in response to twoperiodic input signals A and B being aligned in phase.

Phase detection circuit 600 includes chopper switch 601, delay circuit603, quadrature phase detector input stage circuit 604, inverting delaycircuit 605, switch 606, and quadrature phase detector low pass filter(LPF) output stage circuit 607.

A digital periodic clock signal CLK controls the switching periods andduty cycles of switches 601 and 606. When CLK is in a first logic state,chopper switch 601 transmits signal A directly to the 1 input of phasedetector input stage 604 via conductor 608, and chopper switch 601transmits signal B to an input of delay circuit 603. Delay circuit 603delays signal B by about 90° to generate a delayed version of signal B.The delayed version of signal B is transmitted to the 2 input of phasedetector input stage 604.

When CLK is in a second logic state, chopper switch 601 transmits signalA to the input of delay circuit 603, and chopper switch 601 transmitssignal B directly to the 1 input of phase detector input stage 604 viaconductor 608. Delay circuit 603 delays signal A by about 90° togenerate a delayed version of signal A. The delayed version of signal Ais transmitted to the 2 input of phase detector input stage 604.

Quadrature phase detector input stage 604 generates a phase comparisonvoltage signal VP that is indicative of the phase difference between theperiodic signals at its 1 and 2 inputs. Quadrature phase detector inputstage 604 generates a zero output voltage in VP in response to thesignals at its 1 and 2 inputs being offset in phase by +/−90°. Signal VPis transmitted to an input of inverting delay circuit 605 and to a firstinput of switch 606. Inverting delay circuit 605 inverts signal VP togenerate an inverted signal VPB (VPB=−VP) that is transmitted to asecond input of switch 606.

Switch 606 transmits signals VP and VPB to an input of phase detectorLPF output stage 607 in alternating time intervals in response to clocksignal CLK. Phase detector LPF output stage 607 averages phasecomparison signal VP and its inverse signal VPB to generate an outputvoltage signal OUT that is continuous in time. Circuit 600 generates azero voltage in output signal OUT in response to a phase difference of0° between signals A and B.

The frequency of clock signal CLK is greater than the cutoff frequencyof phase detector LPF output stage 607. Phase detector LPF output stage607 filters out the noise in signals VP and VPB that is added to thesesignals by the switching of switch 606 and the chopping operation of thephase detector.

Using only one quadrature phase detector in phase detection 600 andswitch 601 to alternately switch A and B through delay circuit 603eliminates the possibility of mismatches between two different phasedetectors operating in parallel that can adversely affect the outputresponse. It also removes the area needed to fabricate a secondquadrature phase detector.

In one embodiment, the frequency of clock signal CLK is an integerdivision of the frequency of periodic signals A and B. For example, thefrequency of A and B can be 4 or 8 times the frequency of CLK.

FIG. 6B illustrates one example of a current mode logic (CML) XORcircuit implementation of phase detection circuit 600 shown in FIG. 6A.In phase detection circuit 650 shown in FIG. 6B, phase detector inputstage 604 is implemented by CML XOR pull-down network (PDN) circuit 614and current source 619. Also in circuit 650, switch 606 is implementedby a chopper switch 612, and phase detector LPF output stage 607 isimplemented by resistors 615-616 and capacitors 617-618.

Chopper switch 601 and delay circuit 603 function as described abovewith respect to FIG. 6A. The 1 and 2 inputs of CML XOR PDN 614 functionas the 1 and 2 inputs of phase detector input stage 604. CML XOR PDN 614compares the phases of the periodic signals at its 1 and 2 inputs togenerate differential current signals IP and IPB, which serve the samepurpose as voltage signals VP and VPB in FIG. 6A, but exist in thecurrent domain. Current source 619 provides tail current for CML XOR PDN614 and resistors 615-616.

Clock signal CLK controls the period and the duty cycle of chopperswitch 612. When CLK is in a first logic state, chopper switch 612transmits CML XOR PDN output current IP to output node 621 and outputcurrent IPB to output node 622. When CLK is in a second logic state,chopper switch 612 transmits CML XOR PDN output current IP to outputnode 622 and output current IPB to output node 621.

The output voltages OUT and OUTB of phase detection circuit 650 aregenerated at output nodes 621 and 622, respectively. Output voltages OUTand OUTB function as a differential output voltage signal. Differentialoutput signal OUT/OUTB has a zero voltage in response to a phasedifference of 0° between signals A and B.

Load resistors 615 and 616 are coupled between output nodes 621 and 622,respectively, and a supply line that is at supply voltage VCC.Capacitors 617 and 618 are also coupled between output nodes 621 and622, respectively, and the VCC supply line. Resistors 615-616 andcapacitors 617-618 function as low pass filters that convert theswitched output currents IP and IPB from CML XOR PDN 614 and chopperswitch 612 to output voltages OUT and OUTB.

CML XOR PDN 614 can be, for example, a symmetrical or an asymmetricalpull-down network of n-channel field-effect transistors that perform anXOR Boolean logic function. CML XOR PDN 614 may generate an offset in IPand IPB that is caused by mismatches between transistors in PDN 614 oran asymmetric design of PDN 614. However, any offset caused by PDN 614is canceled out by the averaging function performed by chopper switch612 and the output LPF stage 615-618. Because circuit 650 can functionas intended even with offsets in PDN 614, the area and the complexity ofthe design of PDN 614 can be reduced.

The design of phase detection circuit 650 is merely one example of animplementation of phase detection circuit 600. Phase detection circuit600 can also be implemented using other circuit components. For example,LPF output stage 607 can be implemented using an integrator circuit.

According to an alternative embodiment of phase detection circuit 600,phase detector input stage 604 is a non-ideal zero phase detector thathas a static phase offset. Delay circuit 603 is removed in thisembodiment, and the second output of switch 601 is coupled directly tothe 2 input of input stage 604.

FIG. 7 illustrates another example of a phase detection circuit 700.Phase detection circuit 700 has two sample and hold circuits that sampletwo periodic input signals A and B. Phase detection circuit 700 filtersthe sampled values of the two periodic inputs signals and then subtractsthe filtered sampled values to generate an output phase comparisonsignal. Phase detection circuit 700 functions as a zero phase detectorthat generates a zero output in response to periodic input signals A andB being aligned in phase.

Zero phase detector 700 includes n-channel metal oxide semiconductorfield-effect transistors (MOSFETs) 701-704, capacitors 711-714, anddifferencing amplifier 720. Signal A is provided to a first drain/sourceinput of transistor 701, signal B is provided to the gate of transistor701, and inverse signal /B is provided to the gate of transistor 702.Input signals B and /B are digital periodic signals that areapproximately 180° out of phase with each other.

Transistor 701 and capacitor 711 function as a first sample and holdcircuit.

When signal B is in a logic high state, and signal /B is in a logic lowstate, transistor 701 is on, transistor 702 is off, and the state ofsignal A is stored on capacitor 711. When signal B transitions to a lowlogic state, the last value of signal A is held on capacitor 711. Thus,negative transitions of signal B are used to sample and hold signal A,which also has a negative transition at the same time if A and B have azero phase difference, forming a non-ideal zero phase detector. Thefinite threshold voltage of MOSFET 701, delay in sampling input signal Aonto capacitor 711, and other practical limitations lead to static phaseoffsets in such a phase detector, but the phase detector is relativelyfast and simple to implement.

Transistor 702 and capacitor 712 function as a first switched capacitorsingle-pole low pass filter (LPF) to filter the response of the phasedetector formed by transistor 701 and capacitor 711. When signal B is ina logic low state, and signal /B is in a logic high state, transistor701 is off, transistor 702 is on, and the voltage stored on capacitor711 is averaged with the voltage stored on capacitor 712 based on thecapacitance ratios of capacitors 711 and 712.

Capacitor 712 can have a much larger capacitance than capacitor 711. Forexample, the capacitance of capacitor 712 can be 100 or more timeslarger than the capacitance of capacitor 711. Transistor 702 andcapacitor 712 attenuate high frequency components of the voltage signalstored on capacitor 712. Transistors 701-702 and capacitors 711-712 alsofunction as a non-ideal zero phase detector having a static phaseoffset.

Signal B is provided to a first drain/source input of transistor 703,signal A is provided to the gate of transistor 703, and inverse signal/A is provided to the gate of transistor 704. Input signals A and /A aredigital periodic signals that are approximately 180° out of phase witheach other. It may be desirable to adjust the phase relationship betweensignals B and /B and the phase relationship between signals A and /A byusing early or late phases. For example, signals /A and /B can bedesigned to have a duty cycle that is less than 50%.

Transistor 703 and capacitor 713 function as a second sample and holdcircuit. When signal A is in a logic high state, and signal /A is in alogic low state, transistor 703 is on, transistor 704 is off, and thestate of signal B is stored on capacitor 713. When signal A transitionsto a low logic state, the last value of signal B is held on capacitor713. Thus, negative transitions of signal A are used to sample and holdsignal B, which also has a negative transition at the same time if A andB have a zero phase difference, forming a non-ideal zero phase detector.

Transistor 704 and capacitor 714 function as a second switched capacitorsingle-pole low pass filter to filter the response of the phase detectorformed by transistor 703 and capacitor 713. When signal A is in a logiclow state, and signal /A is in a logic high state, transistor 703 isoff, transistor 704 is on, and the voltage stored on capacitor 713 isaveraged with the voltage stored on capacitor 714 based on thecapacitance ratios of capacitors 713 and 714.

Capacitor 714 can have a much larger capacitance than capacitor 713. Forexample, the capacitance of capacitor 714 can be 100 or more times thecapacitance of capacitor 713. Transistor 704 and capacitor 714 attenuatehigh frequency components of the voltage signal stored on capacitor 714.Transistors 703-704 and capacitors 713-714 also function as a non-idealzero phase detector having a static phase offset.

Differencing amplifier 720 amplifies the difference between the voltagestored on capacitor 712 and the voltage stored on capacitor 714 togenerate an output signal OUT. Because both capacitor voltages aresubject to the same static phase offset from the two non-ideal zerophase detectors, output signal OUT is a phase comparison signal having avoltage that is indicative only of the phase difference between periodicinput signals A and B, and not the discussed static phase offsets. Phasedetection circuit 700 generates a zero voltage in output signal OUT inresponse to a phase difference of 0° between signals A and B.

Phase detection circuit 700 is shown as a single-ended implementation inFIG. 7. According to another embodiment, phase detection circuit 700 cancompare the phases of differential periodic input signals.

The phase detection circuits shown in FIGS. 1, 2A, 3, 4, 5, 6A-6B, and 7can be used in delay-locked loop and phase-locked loop circuits. FIG. 8Aillustrates an example of a delay-locked loop (DLL) circuit 800 that caninclude one of the phase detection circuits shown in FIGS. 1, 2A, 3, 4,5, 6A-6B, and 7. DLL 800 is embedded in an integrated circuit 810. DLL800 includes phase detection circuit 801, loop filter circuit 802, andvariable delay circuit 803. Phase detection circuit 801 can be one ofthe phase detection circuits 100, 200, 300, 400, 500, 600, 650, or 700.

Phase detection circuit 801 compares the phase of a periodic feedbackclock signal FBCLK to the phase of a periodic reference clock signalREFCLK to generate a phase comparison signal VC. Signal VC is indicativeof the phase difference between REFCLK and FBCLK. Loop filter circuit802 filters the phase comparison signal VC to generate a filtered phasecomparison signal VCF.

Variable delay circuit 803 delays REFCLK to generate FBCLK. Variabledelay circuit 803 varies the delay provided to FBCLK relative to REFCLKbased on changes in the filtered phase comparison signal VCF. DLL 800drives the phase difference between FBCLK and REFCLK to 0°. When thephase difference between FBCLK and REFCLK is 0°, DLL 800 maintains thephase of FBCLK constant.

FIG. 8B illustrates an example of a phase-locked loop (PLL) circuit 850that can include one of the phase detection circuits shown in FIGS. 1,2A, 3, 4, 5, 6A-6B, and 7. PLL 850 is embedded in an integrated circuit860. PLL 850 includes phase detection circuit 851, loop filter circuit852, oscillator circuit 853, and divider circuit 854. Phase detectioncircuit 851 can be one of the phase detection circuits 100, 200, 300,400, 500, 600, 650, or 700.

Phase detection circuit 851 compares the phase of a periodic feedbackclock signal FBCLK to the phase of a periodic reference clock signalREFCLK to generate a phase comparison signal VC. Signal VC is indicativeof the phase difference between REFCLK and FBCLK. Loop filter circuit852 filters the phase comparison signal VC to generate a filtered phasecomparison signal VCF.

Oscillator circuit 853 generates a periodic output clock signal OUTCLK.Oscillator circuit 853 varies the frequency of OUTCLK based on changesin the filtered phase comparison signal VCF. Divider circuit 854generates feedback clock signal FBCLK in response to OUTCLK. Dividercircuit 854 divides the frequency of OUTCLK to generate the frequency ofFBCLK. In some embodiments, divider circuit 854 is removed, and thefrequency of FBCLK is equal to the frequency of OUTCLK. PLL 850 adjuststhe phase and the frequency of FBCLK until FBCLK and REFCLK have thesame frequency and are aligned in phase. When FBCLK and REFCLK have thesame frequency and are aligned in phase, PLL 850 maintains the phase andthe frequency of FBCLK constant.

FIG. 9 illustrates an example of a delay-locked loop (DLL) circuit 900that aligns the phase of a feedback clock signal FBCLK with the phase ofa reference clock signal REFCLK using a quadrature phase detector. DLL900 includes a quadrature phase detector circuit 901, ananalog-to-digital converter (ADC) circuit 902, a delay circuit 903, asubtraction circuit 904, a digital accumulator (ACC) circuit 905, amultiplexer circuit 906, a digital gain circuit 907, a digitalaccumulator circuit 908, and digitally adjustable delay circuit 909.Circuits 903 and 904 together form a differentiator.

Quadrature phase detector 901 can be a high-speed phase detector thatconsumes a relatively small amount of power. Quadrature phase detector901 compares the phase of a periodic feedback clock signal FBCLK to thephase of a periodic input reference clock signal REFCLK to generate aphase comparison signal VQ. The voltage of VQ is indicative of the phasedifference between REFCLK and FBCLK. Voltage VQ may represent asingle-ended or differential signal.

Quadrature phase detector 901 generates a zero voltage in VQ in responseto a difference of +or −90° between the phases of FBCLK and REFCLK.REFCLK and FBCLK have the same frequency. 90° refers to one-quarter of aperiod of REFCLK and FBCLK. Quadrature phase detector 901 generates apeak voltage in VQ in response to a phase difference between FBCLK andREFCLK of 0°. DLL 900 is designed to cause the output voltage VQ ofphase detector 901 to converge to a peak voltage that is caused by thephases of FBCLK and REFCLK being in alignment. The peak voltage in VQoccurs at an inflection point in a plot of the output response of VQ.

Phase comparison signal VQ is an analog voltage signal. ADC circuit 902converts analog voltage VQ into a set of digital signals X_(T). Digitalsignals X_(T) are representative of the voltage of VQ. ADC 902 can use,for example, a successive approximation algorithm.

Delay circuit 903 performs a unit time interval delay function on thedigital value of signals X_(T) to generate digital signals X_(T-1).Digital signals X_(T-1) represent the values of signals X_(T) atpreceding time intervals. Subtraction circuit 904 subtracts signalsX_(T-1) from signals X_(T) to indicate whether X_(T) is larger orsmaller than X_(T-1). Thus, the result MSB of the subtraction performedby circuit 904 is indicative of the slope of phase comparison signal VQ.

The MSB output by subtraction circuit 904 is 0 if phase comparisonsignal VQ is increasing, and the MSB output by circuit 904 is 1 if phasecomparison signal VQ is decreasing. Accumulator circuit 905 converts theMSB output of circuit 904 into a single sticky bit STB. Accumulator 905sets the state of sticky bit STB based on the history of the MSB outputof circuit 904. Sticky bit STB is transmitted to a select input ofmultiplexer circuit 906.

Multiplexer 906 transmits signals having a +1 value to digital gaincircuit 907 when the phase comparison signal VQ has been increasing overmultiple sampled values of VQ. Multiplexer 906 transmits signals havinga −1 value to digital gain circuit 907 when the phase comparison signalVQ has been decreasing over multiple sampled values of VQ. Digital gaincircuit 907 sets the gain of the +1 or −1 signals from multiplexer 906to generate scaled output signals that are transmitted to accumulator908. Accumulator 908 converts the output signals of circuit 907 intomulti-bit digital control signals DCS.

Digitally adjustable delay circuit 909 delays input reference clocksignal REFCLK to generate the feedback clock signal FBCLK. FBCLK andREFCLK have the same frequency. The digital control signals DCSgenerated by accumulator 908 control the delay that digitally adjustabledelay circuit 909 adds to FBCLK relative to REFCLK. Digitally adjustabledelay circuit 909 can be, for example, a phase interpolator, a resonantdelay circuit, an adjustable delay chain, or any other suitableadjustable delay circuit. An example of a resonant delay circuit thatcan be used to implement adjustable delay circuit 909 is described incommonly-assigned U.S. provisional patent application 61/252,126, byAryanfar et al., filed Oct. 15, 2009, which is incorporated by referenceherein in its entirety.

When multiplexer circuit 906 transmits a +1 value to circuit 907,control signals DCS cause the delay of adjustable delay circuit 909 toincrease. When multiplexer circuit 906 transmits a −1 value to circuit907, control signals DCS cause the delay of adjustable delay circuit 909to decrease.

DLL 900 causes the phase difference between FBCLK and REFCLK to convergeto 0°, which causes the phase comparison signal VQ to reach a peakinflection point voltage. When the phase comparison signal VQ isdecreasing, DLL 900 adjusts the phase of FBCLK to cause the phasecomparison signal VQ to increase, until phase comparison signal VQreaches a peak voltage. When the phase comparison signal VQ reaches itspeak voltage, DLL 900 maintains the delay that adjustable delay circuit909 provides to

FBCLK at a constant value.

Quadrature phase detector 901 can be implemented, for example, by amixer circuit or by an XOR based phase detector circuit. FIG. 10illustrates a schematic diagram of a differential current mode logic(CML) XOR based phase detector circuit 1000 that can be used as phasedetector 901 in DLL 900. Phase detector 1000 functions as a quadraturephase detector that generates a zero output when the phase differencebetween its two periodic input signals is +/−90°. Phase detector 1000 isa high-speed phase detector that can detect phase differences betweenperiodic signals having large frequencies (e.g., 16 GHz). Phase detector1000 consumes a relatively small amount of power and generates arelatively small amount of jitter in its output signals.

Phase detector 1000 includes resistors 1001-1002 and n-channel MOSFETs1003-1019. Resistors 1001-1002 are coupled to a supply line at a supplyvoltage VCC. The circuit elements of phase detector 1000 are coupledtogether in a symmetrical configuration as shown in FIG. 10.

Phase detector 1000 receives two differential input signals. Signals APand AN are the first differential input signal, and signals BP and BNare the second differential input signal. Signals AP, AN, BP, and BN areprovided to the gates of transistors 1003-1018 as shown in FIG. 10. Ifphase detector 1000 is phase detector 901 in DLL 900, then differentialsignals AP/AN and BP/BN are periodic signals REFCLK and FBCLK.

A constant bias voltage VBN is provided to the gate of transistor 1019.Transistor 1019 provides tail current for phase detector 1000.

Phase detector 1000 performs an XOR Boolean logic function ondifferential input signals AP/AN and BP/BN to generate differentialoutput signal XOR/XNOR. Output voltage XOR is generated at output node1022, and output voltage XNOR is generated at output node 1021.

According to some embodiments, phase detectors 101, 203 and 204, 305 and306, 504, and 604/607 can be implemented using CML XOR based phasedetector 1000. According to other embodiments, phase detectors 101, 203and 204, 305 and 306, 504, and 604/607 can be implemented using anasymmetrical CML XOR based phase detector circuit design having lesstransistors than phase detector 1000.

FIG. 11 is a graph that illustrates the output response of phasedetector 1000 shown in FIG. 10. The vertical axis shown in FIG. 11indicates the voltage of the differential output signal XOR/XNOR ofphase detector 1000. The horizontal axis shown in FIG. 11 indicates thephase difference φ between the differential input signals AP/AN andBP/BN of phase detector 1000 in degrees.

When phase detector 1000 is used in a conventional DLL, the differentialoutput voltage XOR/XNOR of phase detector 1000 converges to a naturallock point of zero volts. As shown in FIG. 11, two of the natural lockpoints occur when the phase difference between differential inputsignals AP/AN and BP/BN is +/−90°, and the differential output voltageXOR/XNOR of phase detector 1000 is zero.

When phase detector 1000 is used as phase detector 901 in DLL 900, thedifferential output voltage XOR/XNOR of phase detector 1000 converges tothe desired lock point shown in FIG. 11. The desired lock point occursat a peak inflection point of the output voltage response of XOR/XNORthat is generated in response to a phase difference of 0° betweendifferential input signals AP/AN and BP/BN.

The circuitry described herein can be used in any suitable integratedcircuit, such as, for example, a memory integrated circuit, a controllerintegrated circuit, a processor integrated circuit, an analog integratedcircuit, a digital integrated circuit, etc.

According to an embodiment, a feedback loop circuit comprises a phasedetector, a loop filter, and a phase adjustment circuit. The phasedetector detects a phase relationship between first and second clocksignals. The loop filter generates an output signal based on an outputsignal of the phase detector. The feedback loop circuit operates suchthat the output signal of the loop filter converges to where an averagevalue of the output signal of the phase detector is at a maximum valueor an inflection point. The phase adjustment circuit adjusts a phase ofthe second clock signal in response to the output signal of the loopfilter. The phase adjustment circuit can comprise a resonant buffercircuit, an oscillator, a delay line, or a phase interpolator circuit.The phase detector can comprise a quadrature phase detector, such as anXOR based phase detector, or a phase mixer circuit. The feedback loopcircuit can be a DLL or a phase-locked loop (PLL). In the case of a PLL,the digitally adjustable delay may be replaced by a digitally controlledoscillator (DCO), such as a resonant tank oscillator or a ringoscillator.

According to another embodiment, a feedback loop circuit comprises aquadrature phase detector, a loop filter, and a phase adjustmentcircuit. The quadrature phase detector detects a phase relationshipbetween first and second clock signals. The loop filter generates anoutput signal based on an output signal of the quadrature phasedetector. The feedback loop circuit operates such that the output signalof the loop filter converges to where the first and the second clocksignals are in phase. The phase adjustment circuit adjusts a phase ofthe second clock signal in response to the output signal of the loopfilter. The loop filter can comprise a differentiator circuit. Thefeedback loop circuit can be a DLL or a PLL.

The foregoing description of the exemplary embodiments has beenpresented for the purposes of illustration and description. Theforegoing description is not intended to be exhaustive or limiting tothe examples disclosed herein. In some instances, certain features ofthe embodiments can be employed without a corresponding use of otherfeatures as set forth. Many modifications, substitutions, and variationsare possible in light of the above teachings, without departing from thescope of the claims.

1. A circuit comprising: a first phase detector generating a first phasecomparison signal that is indicative of a phase difference between firstand second periodic signals, wherein the first phase comparison signalhas a non-zero value in response to first input signals to the firstphase detector being aligned in phase, and wherein the first inputsignals are based on the first and the second periodic signals; a secondphase detector generating a second phase comparison signal that isindicative of a phase difference between the first and the secondperiodic signals, wherein the second phase comparison signal has anon-zero value in response to second input signals to the second phasedetector being aligned in phase, and wherein the second input signalsare based on the first and the second periodic signals; and a combinercircuit that combines the first and the second phase comparison signalsto generate a third phase comparison signal having a zero value when thefirst and the second periodic signals are aligned in phase.
 2. Thecircuit of claim 1 further comprising: a first delay circuit that delaysthe second periodic signal to generate a first delayed signal, whereinthe first input signals to the first phase detector are the firstperiodic signal and the first delayed signal; and a second delay circuitthat delays the first periodic signal to generate a second delayedsignal, wherein the second input signals to the second phase detectorare the second periodic signal and the second delayed signal.
 3. Thecircuit of claim 2 wherein the first delay circuit delays the secondperiodic signal by approximately 90 degrees to generate the firstdelayed signal, wherein the second delay circuit delays the firstperiodic signal by approximately 90 degrees to generate the seconddelayed signal, and wherein the first and the second phase detectors arequadrature phase detectors.
 4. The circuit of claim 2 wherein the firstand the second phase detectors have substantially the same circuitdesigns, and wherein the first and the second delay circuits haveidentical circuit designs.
 5. The circuit of claim 1 wherein thecombiner circuit is a subtraction circuit that subtracts the first phasecomparison signal from the second phase comparison signal to generatethe third phase comparison signal.
 6. The circuit of claim 1 wherein thesecond phase comparison signal is a phase shifted version of the firstphase comparison signal when the first and the second phase comparisonsignals are plotted as a function of a phase difference between thefirst and the second periodic signals.
 7. The circuit of claim 1 whereinthe first and the second phase detectors are quadrature phase detectors.8. The circuit of claim 1 further comprising: a first delay circuit thatdelays the first periodic signal to generate a first delayed signal; asecond delay circuit that delays the second periodic signal to generatea second delayed signal, wherein the first input signals to the firstphase detector are the first delayed signal and the second delayedsignal; a third delay circuit that delays the first periodic signal togenerate a third delayed signal; and a fourth delay circuit that delaysthe second periodic signal to generate a fourth delayed signal, whereinthe second input signals to the second phase detector are the thirddelayed signal and the fourth delayed signal.
 9. The circuit of claim 8wherein the first delay circuit delays the first periodic signal byapproximately 45 degrees to generate the first delayed signal, whereinthe second delay circuit delays the second periodic signal byapproximately −45 degrees to generate the second delayed signal, whereinthe third delay circuit delays the first periodic signal byapproximately −45 degrees to generate the third delayed signal, whereinthe fourth delay circuit delays the second periodic signal byapproximately 45 degrees to generate the fourth delayed signal, andwherein the first and the second phase detectors are quadrature phasedetectors.
 10. The circuit of claim 8 wherein the first and the secondphase detectors have substantially the same circuit designs, wherein thefirst and the fourth delay circuits have substantially the same circuitdesigns, and wherein the second and the third delay circuits havesubstantially the same circuit designs.
 11. The circuit of claim 1wherein the first and the second phase detectors are zero phasedetectors that have systematic static phase offsets, and wherein thefirst input signals are the first and the second periodic signals, andthe second input signals are the first and the second periodic signals.12. The circuit of claim 11 wherein the first phase detector comprises afirst sample and hold circuit that samples the first periodic signalwith the second periodic signal, and wherein the second phase detectorcomprises a second sample and hold circuit that samples the secondperiodic signal with the first periodic signal.
 13. The circuit of claim12 wherein the first sample and hold circuit is coupled to a first lowpass filter circuit, wherein the first sample and hold circuit and thefirst low pass filter circuit generate the first phase comparisonsignal, wherein the second sample and hold circuit is coupled to asecond low pass filter circuit, wherein the second sample and holdcircuit and the second low pass filter circuit generate the second phasecomparison signal, and wherein the combiner circuit is a differencingamplifier that generates the third phase comparison signal based on thefirst and the second phase comparison signals.
 14. The circuit of claim12 wherein the first sample and hold circuit comprises a firsttransistor coupled to a first capacitor, wherein the first periodicsignal is received at a channel input of the first transistor, whereinthe second periodic signal is received at a control input of the firsttransistor, wherein the second sample and hold circuit comprises asecond transistor coupled to a second capacitor, wherein the secondperiodic signal is received at a channel input of the second transistor,and wherein the first periodic signal is received at a control input ofthe second transistor.
 15. The circuit of claim 1 wherein the circuit ispart of a delay-locked loop.
 16. The circuit of claim 1 wherein thecircuit is part of a phase-locked loop.
 17. The circuit of claim 1wherein the circuit is embedded in an integrated circuit.
 18. Thecircuit of claim 17 wherein the integrated circuit is a memoryintegrated circuit.
 19. The circuit of claim 17 wherein the integratedcircuit is a memory controller integrated circuit.
 20. A circuitcomprising: a phase detector generating a phase comparison signal thatis indicative of a phase difference between first and second periodicsignals, wherein the phase comparison signal has a non-zero value inresponse to first and second input signals to the phase detector beingaligned in phase, and wherein the first and the second input signals arebased on the first and the second periodic signals; and an outputcircuit receiving the phase comparison signal and generating an outputthat is indicative of the phase difference between the first and thesecond periodic signals and that has a zero value in response to thefirst and the second periodic signals being aligned in phase.
 21. Thecircuit of claim 20 further comprising: a first chopper switch circuitthat periodically switches the first and the second periodic signals toa first output of the first chopper switch circuit, wherein the firstchopper switch circuit periodically switches the first and the secondperiodic signals to a second output of the first chopper switch circuit,and wherein a signal generated at the first output of the first chopperswitch circuit is the first input signal to the phase detector; and adelay circuit that delays a signal generated at the second output of thefirst chopper switch circuit to generate the second input signal to thephase detector.
 22. The circuit of claim 21 further comprising: a secondchopper switch circuit coupled to an output of the phase detector,wherein the output circuit comprises a load circuit coupled to thesecond chopper switch circuit, wherein the second chopper switch circuitperiodically switches the phase comparison signal and an inverted phasecomparison signal generated by the phase detector to an input of theload circuit.
 23. The circuit of claim 22 wherein the phase detectorcomprises a pull-down network of transistors, and wherein the secondchopper switch circuit is coupled between the load circuit and thepull-down network of transistors.
 24. The circuit of claim 23 whereinthe phase detector is an XOR based phase detector.
 25. The circuit ofclaim 22 wherein the input of the load circuit is a differential input,and the phase comparison signal is a differential signal.
 26. Thecircuit of claim 22 wherein a clock signal controls periodic switchingof both the first and the second chopper switch circuits.
 27. Thecircuit of claim 20 further comprising: a first chopper switch circuitthat periodically switches the first and the second periodic signals toa first output of the first chopper switch circuit, and wherein thefirst chopper switch circuit periodically switches the first and thesecond periodic signals to a second output of the first chopper switchcircuit; and a delay circuit that delays a signal generated at thesecond output of the first chopper switch circuit to generate the secondinput signal to the phase detector.
 28. The circuit of claim 20 furthercomprising: a first chopper switch circuit that periodically switchesthe first and the second periodic signals to a first output of the firstchopper switch circuit, and wherein the first chopper switch circuitperiodically switches the first and the second periodic signals to asecond output of the first chopper switch circuit; a delay circuit thatdelays a signal generated at the second output of the first chopperswitch circuit to generate a delayed signal; and a second chopper switchcircuit coupled to the delay circuit and to the first chopper switchcircuit, wherein the second chopper switch circuit periodically switchesa signal generated at the first output of the first chopper switchcircuit and the delayed signal between inputs of the phase detector togenerate the first and the second input signals to the phase detector,wherein a clock signal controls periodic switching of both the first andthe second chopper switch circuits.
 29. The circuit of claim 21 whereinthe phase detector is a quadrature phase detector, and the delay circuithas a delay of approximately 90°.
 30. The circuit of claim 20 whereinthe phase comparison signal is a differential signal.
 31. The circuit ofclaim 20 wherein the circuit is part of a delay-locked loop.
 32. Thecircuit of claim 20 wherein the circuit is part of a phase-locked loop.33. The circuit of claim 20 wherein the circuit is embedded in anintegrated circuit.
 34. A method comprising: comparing phases of firstand second periodic signals to generate a first phase comparison signalthat has a non-zero value in response to first input signals to a firstphase detector being in phase, and wherein the first input signals arebased on the first and the second periodic signals; comparing phases ofthe first and the second periodic signals to generate a second phasecomparison signal that has a non-zero value in response to second inputsignals to a second phase detector being in phase, and wherein thesecond input signals are based on the first and the second periodicsignals; and combining the first and the second phase comparison signalsto generate a phase comparison output that is indicative of a phasedifference between the first and the second periodic signals and thathas a zero value when the first and the second periodic signals are inphase.
 35. The method of claim 34 further comprising: delaying thesecond periodic signal to generate a first delayed signal, wherein thefirst input signals to the first phase detector are the first periodicsignal and the first delayed signal; and delaying the first periodicsignal to generate a second delayed signal, wherein the second inputsignals to the second phase detector are the second periodic signal andthe second delayed signal.
 36. The method of claim 35 wherein delayingthe second periodic signal to generate a first delayed signal furthercomprises delaying the second periodic signal by approximately 90degrees to generate the first delayed signal, and wherein delaying thefirst periodic signal to generate a second delayed signal furthercomprises delaying the first periodic signal by approximately 90 degreesto generate the second delayed signal.
 37. The method of claim 34wherein combining the first and the second phase comparison signals togenerate a phase comparison output that is indicative of a phasedifference between the first and the second periodic signals and thathas a zero value when the first and the second periodic signals arealigned in phase further comprises subtracting the first phasecomparison signal from the second phase comparison signal to generatethe phase comparison output.
 38. The method of claim 34 furthercomprising: delaying the first periodic signal to generate a firstdelayed signal; delaying the second periodic signal to generate a seconddelayed signal, wherein the first input signals to the first phasedetector are the first and the second delayed signals; delaying thefirst periodic signal to generate a third delayed signal; and delayingthe second periodic signal to generate a fourth delayed signal, whereinthe second input signals to the second phase detector are the third andthe fourth delayed signals.
 39. The method of claim 34 wherein comparingphases of first and second periodic signals to generate a first phasecomparison signal further comprises sampling the first periodic signalwith the second periodic signal to generate the first phase comparisonsignal, and wherein comparing phases of the first and the secondperiodic signals to generate a second phase comparison signal furthercomprises sampling the second periodic signal with the first periodicsignal to generate the second phase comparison signal.
 40. A methodcomprising: comparing phases of first and second periodic signals togenerate a phase comparison signal that has a non-zero value in responseto first and second input signals to a phase detector being in phase,and wherein the first and the second input signals are based on thefirst and the second periodic signals; and generating an output based onthe phase comparison signal that is indicative of a phase differencebetween the first and the second periodic signals and that has a zerovalue in response to the first and the second periodic signals being inphase.
 41. The method of claim 40 further comprising: periodicallyswitching the first and the second periodic signals to a first output ofa first chopper switch circuit and periodically switching the first andthe second periodic signals to a second output of the first chopperswitch circuit, wherein a signal generated at the first output of thefirst chopper switch circuit is the first input signal to the phasedetector; and delaying a signal generated at the second output of thefirst chopper switch circuit to generate the second input signal to thephase detector.
 42. The method of claim 41 further comprising:alternately and periodically switching the phase comparison signal andan inverted version of the phase comparison signal between inputs of aload circuit using a second chopper switch circuit.
 43. The method ofclaim 40 further comprising: periodically switching the first and thesecond periodic signals to a first output of a first chopper switchcircuit and periodically switching the first and the second periodicsignals to a second output of the first chopper switch circuit; anddelaying a signal generated at the second output of the first chopperswitch circuit to generate a delayed signal.
 44. The method of claim 43further comprising: alternately and periodically switching a signalgenerated at the first output of the first chopper switch circuit andthe delayed signal between outputs of a second chopper switch circuit togenerate the first and the second input signals to the phase detector,wherein a clock signal controls periodic switching of both the first andthe second chopper switch circuits.
 45. The method of claim 43 furthercomprising: sampling the phase comparison signal to generate first andsecond sampled signals; and subtracting the first sampled signal fromthe second sampled signal to generate the output.
 46. The method ofclaim 41 wherein delaying a signal generated at the second output of thefirst chopper switch circuit to generate the second input signal to thephase detector further comprises delaying the signal generated at thesecond output of the first chopper switch circuit by approximately 90°to generate the second input signal to the phase detector.